Complementary metal oxide semiconductor (CMOS) technology is the primary technology employed for ultra-large scale integrated (ULSI) circuits. Over the past decades, reduction in the size of CMOS transistors, such as metal oxide semiconductor field-effect transistors (MOSFETs), has been a principle focus of the microelectronics industry. As transistors become smaller, the body thickness of the transistor (or thickness of the depletion layer below the inversion channel) must be scaled down to achieve superior short-channel performance.
In practice, the geometry of the gate and channel can become quite complicated. In one class of the device, a gate may be placed beneath the channel, as well as on top of the channel and its sides, to define a gate-all-around device, such as a gate-all-around MOSFET device. The gate-all-around configuration advantageously significantly increases the extent of the inversion layer. One type of gate-all-around device includes nanowire structures, in which one or more nanowires define the channel or channels of the FET and the gate is structured to wrap around each of the nanowires. However, fabrication of nanowire structures is challenging, and integration of nanowire fabrication techniques into integrated circuit fabrication processes continues to pose several difficulties.